Work

224 Tops/W-Level Analog Computation in Memory Cell Using Hybrid Ferroelectric Tunnel Junction Having Enhanced on-State Conductance

Year: 2025

Type: conference-paper

DOI: 10.23919/vlsitechnologyandcir65189.2025.11074955

Authors: Won-Tae Koo, Sangmin Lee, Hyung Dong Lee, Kayoung Kim, Jae-Gil Lee, Min Yong Lee, Chanbae Kim, Junghun Lee, Ilsik Jang, Youngmo Kim, Seungyeol Oh, Woocheol Lee, Sujin Chae, Ho Jin Cho, Hyejung Choi, Soo Gil Kim, Seho Lee, Jaeyun Yi, Youngman Cho, Seon Yong Cha

Institution: SK Hynix (South Korea)

Language: English

Topic: Ferroelectric and Negative Capacitance Devices

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4412965901

FWCI: 2.325

Cites: 4

Cited by: 1

Related to: 10