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A 31.5-36 GHz Low-Spur Gain-Boosting Charge-Sharing Locking PLL with 54fs Jitter

Year: 2025

Type: conference-paper

DOI: 10.23919/vlsitechnologyandcir65189.2025.11074797

Authors: Chawin Khongprasongsiri, Sayan Kumar, Patchara Sawakewang, Robert Bogdan Staszewski, Teerachot Siriburanon

Institution: University College Dublin

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4412965908

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