Process Insights into 3D-DRAM with Vertical Bit Line and Scalable GAA Transistor
Year: 2025
Type: conference-paper
Abstract: A novel 3D-DRAM integration flow with vertical bit line and gate-all-around (GAA) transistor is successfully demonstrated. The process modules are thoroughly described along with the challenges and optimization. The morphological integrity and electrical functionality of GAA select transistors with monocrystalline Si channel are demonstrated. TCAD modeling predicts scaling possibilities with this architecture, corroborating its suitability for future DRAM implementation.
Authors: N. Rassoul, L. A. Labbate, G. Eneman, A. Fantini, R. Ritzenthaler, J. Loyo Prado, R. Loo, W. Devulder, E. Dupuy, T. Peissker, A. Pacco, H. K. Raut, P. Eyben, E. Canga, E. Rosseel, A. Sharma, H. Oh, Y. Rawal, M. Beggiato, J. Kim, Y. Jiang, A. P. Milenin, S. Subhechha, J. Mitard, D. Crotti, I. Lee, A. Belmonte, G. S. Kar
Institution: IMEC
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4412965963