Work

SRAM Scaling Opportunities Below .01 \mu ~\mathrm{m}^{2}$ Using Double-Row CFET Architecture with Wordline-Folded Bitcell Design for Performance Optimization

Year: 2025

Type: conference-paper

DOI: 10.23919/vlsitechnologyandcir65189.2025.11075033

Authors: D. Abdi, G. Hellings, J. Boemmels, F. G-Redondo, L. Verschueren, A. Sharma, H. Kükner, M. G-Bardon, J. Ryckaert

Institution: IMEC

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4412966142

FWCI: 6.975

Cites: 1

Cited by: 3

Related to: 10