Novel Ultra-Thin Transistor Layer Transfer (TLT) Technology for Demonstrating Wafer-Level nm-Scale 3-Layer Stacking to Enable Multi-Tier Transistors and Backside PDN of a 3D Vertical FET Architecture
Year: 2025
Type: conference-paper
Authors: C.-L. Lu, Hankel C.-H. Chang, Y.-C. Lin, P.-R. Ni, C.-H. Chuang, H. Henck, C.-Y. Chuang, S.-C. Lin, H.-S. Huang, L.-H. Chiu, Y.-C. Sun, K.-Y. Shih, I. Radu, Bich-Yen Nguyen, S.-Z. Chang
Institutions: Powerchip (Taiwan), Soitec (France)
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4412966393