Work

Efficient Power-and Area-Optimized 800-Spin Ising Chip for Solving Combinatorial Optimization Problems Using Multi-Run Decremental Annealing

Year: 2025

Type: article

Source: IEEE Internet of Things Journal

DOI: 10.1109/jiot.2025.3595927

Authors: Yuan-Ho Chen, Yu-Jie Yen, Chin-Fu Nien, Chao-Sung Lai

Institutions: National Taiwan University of Science and Technology, Chang Gung University, National Yang Ming Chiao Tung University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funder: National Science and Technology Council

Awards: G539557216, G5430820301

OpenAlex ID: W4412984977

FWCI:

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