Real-Time In-Network Machine Learning on P4-Programmable FPGA SmartNICs with Fixed-Point Arithmetic and Taylor Approximations
Year: 2025
Type: conference-paper
Abstract: As machine learning (ML) applications become integral to modern network operations, there is an increasing demand for network programmability that enables low-latency ML inference for tasks such as Quality of Service (QoS) prediction and anomaly detection in cybersecurity. ML models provide adaptability through dynamic weight adjustments, making Programming Protocol-independent Packet Processors (P4)-programmable FPGA SmartNICs an ideal platform for investigating In-Network Machine Learning (INML). These devices offer high-throughput, low-latency packet processing and can be dynamically reconfigured via the control plane, allowing for flexible integration of ML models directly at the network edge. This paper explores the application of the P4 programming paradigm to neural networks and regression models, where weights and biases are stored in control plane table lookups. This approach enables flexible programmability and efficient deployment of retrainable ML models at the network edge, independent of core infrastructure at the switch level.
Authors: Mohammad Firas Sada, John Graham, Mahidhar Tatineni, Dmitry Mishin, Thomas DeFanti, Frank Würthwein
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Funder: National Science Foundation
Awards: CI-New: Cognitive Hardware and Software Ecosystem Community Infrastructure (CHASE-CI), Towards Deploying a Science-Driven Regional Interoperable Science DMZ, CC* NPEO: Toward the National Research Platform, CCRI: ABR: Cognitive Hardware and Software Ecosystem Community Infrastructure (CHASE-CI), Category II: A Prototype National Research Platform, CC*DNI DIBBs: The Pacific Research Platform, CCRI: ENS: Cognitive Hardware and Software Ecosystem Community Infrastructure (CHASE-CI)
OpenAlex ID: W4413059441