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Fast and Effective Logic Gate Sizing Based on Heterogeneous Graph Neural Network

Year: 2025

Type: conference-paper

Source: International Symposium of Electronics Design Automation (ISEDA)

DOI: 10.1109/iseda65950.2025.11101548

Authors: Yuhan Dong, Junming Jiao, Han Zhang, Yusen Qin, Zeyuan Deng, Xu Cheng, Peng Cao

Institution: Southeast University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: National Natural Science Foundation of China, Fundamental Research Funds for the Central Universities

OpenAlex ID: W4413120706

FWCI:

Cites: 17

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Related to: 10