Year: 2025
Type: conference-paper
Abstract: To address the need for high performance and low power in edge AI scenarios, this paper proposes a domestically developed smart chip acceleration architecture. It features heterogeneous computing units, a configurable on-chip interconnect, and multi-level energy optimization, enabling balanced computational density and power control with broad algorithm compatibility. The design integrates core modeling, dynamic scheduling, clock gating, DVFS, and data flow reconfiguration to enhance energy efficiency. Experimental results demonstrate superior throughput and power control over comparable chips in typical AI tasks, highlighting strong application potential.
Authors: Feng Chen, Hongjing Liang, Lan Yue, Guoping Xu, Shangxi Li
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4413144273