HGPplace: Hierarchical Chip Layout Optimization Combining Graph Convolutional Networks and Polygon-Aware Placement
Year: 2025
Type: conference-paper
Authors: Jianguo Hu, Ye Wang, Shengzhi Shen, Yuhe Wang
Institution: Sun Yat-sen University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4413206090