Work

An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving −251.9 dB FOM Jitter-N

Year: 2025

Type: article

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2025.3598334

Authors: Sirou Li, Rongjin Xu, Weijia Zeng, Kaiyun Cao, Heyu Ren, Xing Wu, Liangjian Lyu, C.-J. Richard Shi

Institutions: Fudan University, East China Normal University, University of Washington

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funders: National Natural Science Foundation of China, Science and Technology Commission of Shanghai Municipality

Awards: G3654611107, G8551726186

OpenAlex ID: W4413349612

FWCI:

Cites: 41

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Related to: 10