Assessing the impact of process and design variations on reliability of complementary FET
Year: 2025
Type: article
Abstract: This paper comprehensively analyzes the reliability concerns of the Complementary FET (CFET), engrossing the design parameters and the variability effects. The impact of process-induced variabilities, such as random dopant distribution (RDD), line edge roughness (LER), and metal gate granularity (MGG), is extensively studied through well-calibrated TCAD models. Variation aware compact model based statistical analysis is used to analyze 100 random device samples, which shows a significant spread in the I DS -V GS curve (transfer characteristics). Electrical performance based on the grain size and fin width is also analyzed on both n and p-type device. Therefore, the variation in threshold voltage (V th ) is used to predict the early aging of the devices.
Source: Solid-State Electronics
Authors: Ankit Dixit, Sandeep Kumar, Naveen Kumar, Deven H. Patil, S. Dasgupta, Navjeet Bagga, Luiz Felipe Aguinsky, Vihar Georgiev
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
Estimated APC paid: $2,410
OpenAlex ID: W4413854189