Work

Layer-Constrained GNR Area Routing With CNT-Via Insertion for Via Minimization

Year: 2025

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2025.3604646

Authors: Jin-Tai Yan, Chia-Heng Yen

Institutions: Tainan National University of the Arts, National Taiwan Ocean University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4413887310

FWCI:

Cites: 28

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Related to: 10