Development of a Novel Warpage Control Method for Epi-Ready 4H-SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces
Year: 2025
Type: article
Abstract: We have demonstrated a novel process that precisely controls the wafer bow, a key parameter of overall warpage, of 4H-SiC wafers to any desired value by integrating a thermal sublimation process, Dynamic AGE-ing® (DA), immediately prior to the CVD epitaxial process. This method achieves atomic-level flatness of the CMP-finished surface independent of the growth and etching amounts, while concurrently eliminating sub-surface damage (SSD). When DA is applied to simultaneously etch the Si-face and grow the C-face, the wafer bow decreases linearly with increasing C-face growth. In wafers with poorer mechanical processing quality, an increase in bow is observed for C-face growth below 120 nm, likely due to the relaxation of SSD on that side. The process also removes SSD from the Si-face, ensuring that both sides are sufficiently cleared of damage. Furthermore, for wafers with an initially negative bow, simultaneous Si-face growth and C-face etching using DA produces a linear increase in bow. By applying these processes, we successfully adjusted the bow to –0.4 µm on an 8-inch wafer that initially measured –12.0 µm. These results indicate that, regardless of the initial bow severity, precise control of the wafer bow can be achieved without adversely affecting subsequent CVD epitaxy processes by appropriately managing the growth layer thicknesses on both faces using DA.
Source: Materials science forum
DOI: 10.4028/p-js5aam
Authors: Daichi Dojima, Seyoon Jeong, Kohei Toda, Tadaaki Kaneko
Institution: Kwansei Gakuin University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4413987013