PARS: A Layered Hardware Obfuscation Platform for Resilience and Secure Collaborative Multi-Module Designs
Year: 2025
Type: conference-paper
Abstract: As hardware design becomes outsourced, protecting intellectual property (IP) from reverse engineering and counterfeiting is a challenge. Logic locking provide a promising solution, but existing approaches fail to balance security, performance, and scalability. We present PARS, a scalable obfuscation platform that integrates locking techniques tailored to different hardware granularity: standalone IPs, multi-module, and Network-on-Chip (NoC) communications. PARS balances overhead and security (ranging from standalone to multi-module systems and networked architectures) to defeat SAT-based, approximate, and learning-based deobfuscation attacks and is a well-suited solution for large designs.
Institutions: National University of Singapore, University of Tehran
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Funder: Ministry of Education, India
OpenAlex ID: W4414109599