Work

DAMIL-DCIM+: Automated Dataflow-Aware Layout Synthesis for Digital CIM With Self-Assembled Bitcell Units and MILP-Based Optimization

Year: 2025

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2025.3608064

Authors: Chuyu Wang, Xinglong Yan, Zecheng Xu, Ke Hu, Keren Zhu, Shuo Li, Fan Yang, Xuan Zeng

Institution: Fudan University

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

Funders: National Natural Science Foundation of China, State Key Laboratory of Intelligent Technology and Systems

Awards: G2453586068, G3495785756, G4650080616, G6135847747, G7097358612, G7203856515, G8453336779

OpenAlex ID: W4414165665

FWCI:

Cites: 19

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