Signal Integrity Study of a Panel Level Package Based on Simulation-Measurement Correlations
Year: 2025
Type: article
Abstract: In this paper, we studied on the signal integrity of a novel 2.3D package platform, called the panel level package (PLP) interposer system. We adopted a simple model which consists of two dimensional transmission line models and fitted parasitic self/mutual inductances and capacitances. Our model is then correlated with the S-parameter model extracted from the real design and the measurement of the fabricated sample. The results show strong correlation in terms of return loss and time domain reflectometry (TDR). The signal integrity of the conventional package based on the Ajinomoto build-up film (ABF) substrate is compared with that of the PLP interposer system. We varied parameters including trace geometry, loss tangent, and parasitic capacitance in our model to improve the signal integrity of the PLP interposer system compared to conventional package. By increasing the cross sectional area of the signal trace and decreasing the parasitic capacitances, the signal integrity of the PLP interposer system can be enhanced to be comparable to the conventional package up to 20GHz, and can be even better in higher frequency ranges.
Author: Sangkyu KIM
Institution: Hongik University
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4414193327