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A 2–2.65-GHz Dual-Core VCO With High- Linearity Varactor Array and High- Q Switched Capacitor Bank Achieving −128 dBc/Hz Phase Noise at 1 MHz Offset

Year: 2025

Type: article

Source: IEEE Microwave and Wireless Technology Letters

DOI: 10.1109/lmwt.2025.3604389

Authors: Bo Cheng, Jiangtao Xu, Huanhuan Qi, Yong Dai, Hui Cao, Jia Shen, Hong Zhang

Institution: Xi'an Jiaotong University

Language: English

Topic: Radio Frequency Integrated Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4414229386

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Cites: 13

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