Year: 2025
Type: article
Abstract: Ensuring the integrity of scan chains in Very Large Scale Integration (VLSI) designs is crucial for hardware security and intellectual property (IP) protection. This work presents a Graph Neural Network (GNN)-based approach for optimising scan chains while simultaneously embedding a robust watermark to authenticate the design. The primary objective is to minimise transition density in scan chains, reducing power consumption while ensuring watermark resilience against adversarial attacks. Scan chain optimization is a crucial aspect of VLSI testing, aimed at minimizing power consumption while ensuring testability. Traditional approaches perform scan chain reordering and watermark embedding as separate steps, often leading to suboptimal solutions in terms of both security and power efficiency. In this work, a unified framework is proposed, where scan chain optimization and watermark embedding are integrated into a single-step process, leveraging Graph Neural Networks (GNNs). By formulating the scan chain as a weighted graph, the optimization is driven by transition density minimization while simultaneously embedding a cryptographic watermark within edge weights. This ensures that the scan chain remains resistant to adversarial modifications while achieving power-efficient reordering. The proposed methodology employs PyTorch Geometric-based GNN models to extract spatial, temporal, and structural features from scan chain graphs. The methodology is validated on the ISCAS-89 benchmark suite, and the results demonstrate a significant reduction in transition density across multiple circuits.
DOI: 10.1145/3769115
Authors: Ashwin CS, Suchismita Roy
Institution: National Institute of Technology Durgapur
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4414374656