Work

Optimization of small-step simulation based on labVIEW FPGA

Year: 2025

Type: article

Abstract: • In the Hardware-in-the-Loop (HIL) simulation experiments, the Virtual Instrument (VI) environment in LabVIEW provides inherent parallel execution features, which align well with the parallel processing capability of Field Programmable Gate Arrays (FPGAs). Therefore, this study employs LabVIEW FPGA technology to implement and validate the proposed switch modeling method within the HIL simulation framework. • Specifically, a DC chopper circuit is modeled using both the Average Discrete Circuit (ADC) method and the Generalized Average Discrete Circuit (GADC) method, while the effectiveness of the Historical Current Recursive Iteration (HCRI) method is further evaluated for improving the accuracy of switch-state iterations. The HIL simulation results obtained on the LabVIEW FPGA platform demonstrate that the conventional ADC method exhibits noticeable oscillations and switching losses during switch modeling. In contrast, the GADC method achieves significant improvements in suppressing such oscillations. Building upon the GADC-based model, the study further applies the HCRI method, which is validated to be effective in reducing switching losses. • This work and its findings are supported by the State Grid Jiangsu Electric Power Co., Ltd. Science and Technology Project (Grant number: J2024072). To meet the requirements of hardware-in-the-loop (HIL) simulation, constant admittance modeling is a widely used approach for the discretization of power electronic converters. This paper investigates the discretization of power electronic energy storage components and the switch equivalent modeling based on the Associated Discrete Circuit (ADC) method. In addition, a Generalized Average Discrete Circuit (GADC) technique and a Historical Current Recursive Iteration (HCRI) method are employed to enhance the efficiency of small time-step simulations and to reduce the virtual power loss of switching devices. The proposed approach is validated through iterative simulations of a Buck converter constant admittance model, implemented in a LabVIEW-based host computer environment. The results demonstrate that, compared with conventional constant admittance modeling, the GADC and HCRI methods achieve significant improvements in power loss suppression and accuracy optimization for switch modeling.

Source: Results in Engineering

DOI: 10.1016/j.rineng.2025.107344

Authors: Lyu Shukang, Yuan Xiaodong, Wang Mingshen, Zeng Fei, Zhu Changyu, Chen Yihan

Institutions: State Grid Jiangsu Electric Power (China), Nanjing University of Posts and Telecommunications

Language: English

Topic: Real-time simulation and control systems

Subfield: Control and Systems Engineering

Field: Engineering

Domain: Physical Sciences

SDGs: Industry, innovation and infrastructure, Affordable and clean energy

Open Access status: gold

Estimated APC paid: $1,940