Designing of AES-128 Encryption Algorithm Using System Verilog VLSI
Year: 2025
Type: conference-paper
Authors: Tarun Sai Gampala, Ashok Chakravarthy Pamarthy, C Sudhakara Reddy
Institution: VIT-AP University
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4414433404