Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application
Year: 2025
Type: article
Source: Physica Scripta
Authors: Vinaya S J, Rathnamala Rao, K S Nikhil
Institution: National Institute of Technology Karnataka
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4414452480