Design of a Low-Power 64-bit ALU Using Vedic Multiplication, Vinculum Encoding, and Reversible Logic on FPGA
Year: 2025
Type: conference-paper
Authors: B S Balaji, Safina Taj, A S Smitha, S B Manoj Kumar, G Manjunatha, K Ramya
Institutions: Adichunchanagiri University, PES University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4414463922