RTL to GDSII: Design and Physical Implementation of a 32-bit RISC-V Floating-Point Co-Processor Using Verilog and Cadence Tools
Year: 2025
Type: conference-paper
Authors: Chandrashekar M Patil, A Geethashree, R Srinivasa, R Rakshith Yadav, S Ajay H, S Dravid
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4414464635