Work

CMOS back-end-of-line integration of bilayer ferroelectric tunnel junction in 1-transistor-1-capacitor circuit

Year: 2025

Type: article

Abstract: Ferroelectric tunnel junction (FTJ) devices based on ferroelectric Hf0.5Zr0.5O2 (HZO) have recently gained significant interest as CMOS back-end-of-line integrable low power non-volatile memories for neuromorphic computing applications. In this paper, we demonstrate integration of metal-ferroelectric- dielectric-metal bilayer FTJ devices in the back-end-of-line of a 180 nm CMOS technology chip. We present electrical characteristics of the integrated FTJ devices, including the polarization switching and resistance switching behavior with an ON/OFF current ratio of ∼ 18, and an ON current density of ∼ 24.5 μA/cm 2 at a read voltage of 1.8 V. Furthermore, we also demonstrate a 1-transistor-1-capacitor (1T1C) circuit by connecting a back-end FTJ device with a front-end nMOS transistor, which amplifies the ON current of the FTJ device by 2.6 times. Thus, we show the basic building block for the integration of HZO-based FTJ devices for neuromorphic applications.

Source: Solid-State Electronics

DOI: 10.1016/j.sse.2025.109255

Authors: Keerthana Shajil Nair, Muhammad Hamid Raza, Catherine Dubourdieu, Veeresh Deshpande

Institutions: Helmholtz-Zentrum Berlin für Materialien und Energie, Freie Universität Berlin

Language: English

Topic: Ferroelectric and Negative Capacitance Devices

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

Estimated APC paid: $2,410

Funders: European Commission, Horizon 2020 Framework Programme, Horizon 2020