Work

Addition of CXL memory pool to increase LLM training check-pointing frequency

Year: 2025

Type: conference-paper

Source: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)

DOI: 10.1109/aicas64808.2025.11173088

Authors: Kiran Gunnam, Prasad Chandrashekara, Murali Kothandapani, Rajesh Bhagwat, Priyanshi Jain

Institution: Micron (United States)

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4414494300

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Cites: 1

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