Work

Reconfigurable Dataflow and Tile Shape Optimization in SystemC-Based NoC of 1D PE Array Simulators integrated with TVM

Year: 2025

Type: conference-paper

Source: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)

DOI: 10.1109/aicas64808.2025.11173164

Authors: Yu-Jen Chang, Ching-Te Chiu, Tzu-Chun Huang

Institution: National Tsing Hua University

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4414499710

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Cites: 21

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