A 107 TOPS/W Instruction Controlled Scalable 8b Precision Analog In-Memory Computing Core with Flexible Kernel Routing for Embedded Applications
Year: 2025
Type: conference-paper
Abstract: This work presents an instruction-controlled analog In-Memory Computing (IMC) core to compute dot-product kernels of varying lengths and precisions parallelly, while achieving an energy efficiency of 107 TOPS/W at 8b precision. This is achieved by a combination of configurable multi-bit multiply-accumulate cells, low energy SAR ADCs with input gain control, and a novel kernel output routing approach. Using this IMC core, a full-fledged multi-core inference accelerator ASIC has been developed that achieves the target accuracy for a Voice Activity Detection usecase over PVT variations.
Authors: Bijoy Kundu, Roland Müller, Yogesh Ramesh Patil, Ralf Brederlow
Institution: Fraunhofer Institute for Integrated Circuits
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Funder: European Commission
OpenAlex ID: W4414500031