Resource efficient design of 16 x 16 multiplier by Block RAM generalized to n x n multiplier realized in FPGA
Year: 2025
Type: article
Abstract: Signal processing and image processing applications demand an efficient and high speed multiplier. It aids in achieving the overall performance of a particular application. Conventionally, multiplication is achieved with the support of an addition operation. Field Programmable Gate Array (FPGA) based multiplier also utilizes adder elements in its design. This work has proposed a resource optimized solution for multiplication using Block RAM (BRAM), an FPGA hardware resource. It generates partial product by shifting. Shifting a number by ‘1’ bit position to the left is equivalent to its multiplication by 2. FPGA logic identifies binary ‘1’ and its bit position in the 16-bit ‘multiplier’, left shifts the 16-bit ‘multiplicand’ according to the bit position. 16-bit ‘multiplicand’ is converted into 32-bit by adding suitable number of ‘0’s both on least significant bit and most significant bit side. This results in 16 partial products of 32-bit. The design develops a 4-bit adder using BRAM. Suitable port mapping of 4-bit adder produces 8-bit / 16-bit / 32-bit adders. Thus designed 32-bit BRAM adder performs concurrent addition in four stages and releases the output of multiplication of two 16-bit numbers. The delay time of 16-bit multiplier, synthesized for xc7v2000t-2fhg1761 chip, has been identified as 3.070ns. The design utilized only 78 and 203 number of lookup tables (LUT) and BRAMs respectively. The proposed idea is valid for the design of n x n multiplier when the HDL logic is modified for ‘n’ times shifting and 2n-bit adder circuit.
DOI: 10.54392/irjmt2556
Authors: Dhanabalan G, Michael Rajan H.B, Ashok R
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4414516238