FPGA based UART Design: Simulation, Synthesis & System Verilog functional verification
Year: 2025
Type: conference-paper
Authors: Vikash Prajapati, Alpana Pandey
Institution: Maulana Azad National Institute of Technology
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4414539357