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Low Complexity Three’s Complement Parallel Multiplier Using Special Operators of Ternary Logic

Year: 2025

Type: article

Source: IEEE Transactions on Circuits & Systems II Express Briefs

DOI: 10.1109/tcsii.2025.3615737

Authors: L. Hemanth Krishna, B. Srinivasu, K. Sridharan

Institutions: Indian Institute of Technology Mandi, Indian Institute of Technology Madras

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4414603071

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Cites: 20

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