An MLIR-Based Compilation Framework for Control Flow Management on Coarse-Grained Reconfigurable Arrays
Year: 2026
Type: article
Abstract: Coarse-Grained Reconfigurable Arrays (CGRAs) present both high flexibility and efficiency, making them well-suited for the acceleration of intensive workloads. Nevertheless, a key barrier toward their widespread adoption is posed by CGRA compilation, which must cope with a multi-dimensional space spanning both the spatial and the temporal domains. Indeed, state-of-the-art compilers are limited in scope, as they mostly handle dataflow while providing little or no support for control flow. Hence, they mostly focus on mapping single loops and/or delegate the management of control-flow divergences to ad hoc hardware units. Conversely, in this article, we show that control flow can be effectively managed and optimized at the compilation level, enabling a broad set of applications to be targeted while remaining hardware-agnostic and achieving high performance. We embody our methodology in a modular compilation framework consisting of transformation and optimization passes, enabling support for applications with arbitrary control flows running on homogeneous CGRA meshes. We also introduce a novel mapping methodology that serves as a compilation backend, addressing limitations in available CGRA hardware resources and ensuring a feasible solution during compilation. Our framework achieves up to 2.1 \(\times\) runtime speed-up over state-of-the-art approaches, purely through compilation optimizations.
DOI: 10.1145/3828545
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W4414690751