Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS
Year: 2025
Type: article
Abstract: This article introduces two comparators featuring a dynamic-bias preamplifier and self-clocked latches, tailored for ultra-low-power and medium-speed applications with$\mu $V input-referred noise (IRN). The proposed self-clocked latches are activated by the preamplifier outputs and therefore operate with a lower common-mode current, which in turn minimizes the crowbar current that is typically present during the comparison phase in conventionally clocked latches. The proposed comparators do not require an additional clock phase for the latch, thereby reducing the clock drive power consumption for systems employing multiple latches, e.g., in ADCs or memories. The absence of an additional clock phase for latching makes them robust toward clock skews, similar to the “StrongARM comparator.” This article also presents an exhaustive overview of the prior art, the “Schinkel comparator,” and its bottlenecks when optimizing for low-noise low-power applications, thereby motivating the importance of self-clocked latches for such applications. This article also discusses the noise–energy–delay design tradeoffs of the proposed dynamic-bias self-clocked (DBSC) comparators. Fabricated in a 65-nm CMOS process along with a standard Schinkel comparator, the two proposed designs exhibit an IRN of 320 and$460~\mu $V while consuming approximately 40fJ of energy per comparison from a 1.2-V supply. The measured CLK-OUT delay stands roughly at 0.5 ns. The results indicate a$2\times $enhancement in energy efficiency and a$3.7\times $and$2.6\times $reduction in IRN with a$2.5\times $increment in CLK-OUT delay for similar differential input voltages when compared to the “Schinkel comparator.”
Institution: University of Twente
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
Award: G3828550083
OpenAlex ID: W4414693323