Year: 2025
Type: preprint
Abstract: This article introduces a novel memristor emulator circuit, the first to employ a single MOSFET and a capacitor, achieving high-frequency operation of approximately 50 MHz. The MOSFET operates in the saturation region, with the gate and drain terminals shorted in both configurations, enabling it to function as a current source that charges the capacitor. The proposed emulator demonstrates ultra-low average transient power consumption of 33 µW and 28 µW for NMOS and PMOS-based designs, respectively, using 180 nm SCL parameters in Cadence Virtuoso. The circuit's performance is validated through various analysis, including frequency variation, transient response, non-volatile behavior, and process variation. Furthermore, the memristor layout is designed, and a comparison of pre-layout and post-layout simulation results is presented. Furthermore the proposed memristor emulator circuit is experimentally validated using off-the-shelf components. Finally, a neuron circuit based on the single-transistor memristor emulator is implemented, with performance evaluations showing a layout area of 3369.72 µm², energy per spike as low as 4.073 pJ, and power consumption of 7.31 µW.
Authors: Arun Kalakola, Basit Shafat Makhdoomi, Rahul Ranjan, Rahul Ranjan, Rajeev Kumar Ranjan, Rajeev Kumar Ranjan, Shahram Minaei
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4414798121
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