Simulating and Optimizing Tapped Delay Lines for Time-to-digital Converters in FPGA using a Precision Model based on Circuit Characteristics
Year: 2025
Type: preprint
Source: SSRN Electronic Journal
DOI: 10.2139/ssrn.5571956
Authors: Julien Rossignol, Daehee Lee, Sun Il Kwon
Institution: University of California, Davis
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4414860331