Verilog Code Generation of Hierarchical Design Using LLMs
Year: 2025
Type: conference-paper
Authors: Geuna Chang, Shilong Zhang, Seohyun Kim, Woojin Kim, Youngsoo Shin
Institution: Korea Advanced Institute of Science and Technology
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4415003314