Work

HR2: A PVT Aware Hierarchical RL Based Sizing Framework for Robust Analog Circuit Design

Year: 2025

Type: conference-paper

DOI: 10.1109/mlcad65511.2025.11189231

Authors: Jaeheon Jung, Dongwoo Lew, Jangseok Yu, Jongsun Park

Institution: Korea University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: National Research Foundation of Korea

OpenAlex ID: W4415003352

FWCI:

Cites: 25

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