Optimizing RTL-Based FPGA Designs for ECU Performance Enhancement: Impact of Hierarchical Flattening Using Xilinx Vivado
Year: 2025
Type: conference-paper
Authors: Pulimi Mahesh, M Suresh Chinnapamthy, M Parthiban, Rr Rajarajavigraman, Suhaib Akthar, S Yeswanth
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4415004559