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Architecture and Energy Efficiency Optimization of Neural Network Accelerator Based on RISC-V Instruction Set Extension

Year: 2025

Type: conference-paper

Source: IEEE International Conference on Computer Communication and Artificial Intelligence (CCAI)

DOI: 10.1109/ccai65422.2025.11189847

Authors: Chang Liu, Biao Pan, Zhencheng Chen, WeiXin Li, He Jiang

Institution: Beihang University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4415108315

FWCI: 7.075

Cites: 12

Cited by: 3

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