Year: 2025
Type: article
Abstract: Ensuring the security of images transmitted openly is critical due to their high susceptibility to unauthorized access. To mitigate such risks, employing data security measures is essential. With the increasing importance of data security in today's digital age, Data Encryption Stand-ard (DES) stands out as a notable block cipher technique for encrypting and decrypting data. Protecting sensitive information is crucial in embedded applications. Implementing cryptographic algorithms on programmable devices like Field Programmable Gate Arrays (FPGAs) combines the physical security of hardware solutions with the speed superiority over software-based approaches. FPGAs offer flexibility like software applications, with the added advantage of being reprogrammable to adapt to different cryptographic algorithms or modifications within the same algorithm, ensuring robust data protection. This work introduces a hardware-oriented approach to executing the DES algorithm using FPGAs. The approach adopted utilizes an iterative loop process with a 128-bit key size, leveraging a lookup table based on S-boxes. Simulation waveforms confirm that the FPGA-based implementation meets the desired specifications, showcasing high throughput. The research highlights a novel hardware-based version of the Triple DES encryption algorithm that achieves high-speed performance with minimal hardware requirements.
DOI: 10.14419/4x2x0830
Authors: Prakash Marakumbi, Satish Bhairannawar
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W4415193871
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