Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials
Year: 2026
Type: article
Abstract: Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source-drain contact resistance. Although two-dimensional semiconductors offer excellent electrostatic control, their interfaces with gate dielectrics and contact metals often form a van der Waals (vdW) gap that affects device performance and acts as a tunneling barrier with a low dielectric constant. While this reduces dielectric leakage, it increases metal-channel contact resistance and introduces a parasitic series capacitance to the gate. We quantified the trade-off between leakage suppression and electrostatic and contact-resistance scaling limits. As a result of this trade-off, many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. Zipper-like interfaces, where quasi-covalent bonding removes the vdW gap without creating dangling bonds, offer a path toward ultrascaled transistor designs.
Source: Science
Authors: Mahdi Pourfath, Tibor Grasser
Institution: TU Wien
Language: English
Subfield: Materials Chemistry
Field: Materials Science
Domain: Physical Sciences
Open Access status: hybrid
Award: G6477255498
OpenAlex ID: W4415254728