Work

Design and Simulation of a 64 Gb/s PAM-4 Wireline Receiver in 22 nm CMOS

Year: 2025

Type: conference-paper

DOI: 10.1109/prime66228.2025.11203302

Authors: A. Cortiula, D. Scubla, S. Murra, D. Menin, A. Bandiziol, F. Driussi, P. Palestri

Institutions: University of Udine, Infineon Technologies (Austria), University of Modena and Reggio Emilia

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Infineon Technologies

OpenAlex ID: W4415399822

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