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Efficient and Effective E-graph-based Logic Optimization

Year: 2025

Type: article

Abstract: Recent efforts of applying e-graphs in logic synthesis have shown promising results. Nevertheless, e-graph-based gate-level logic optimization suffers from inefficiency and limited extraction quality. In this article, we propose a fast parallel e-matching algorithm for speeding up e-graph rewriting, and an efficient netlist extraction framework with high quality of results in both area and delay. Experiments show that e-graph rewriting can be accelerated by up to 8.3× over a high-performance e-graph library, and our extraction framework achieves 11.0% and 1.0% improvements in size and level on average, compared to the best results of the state-of-the-art netlist extraction method.

Source: ACM Transactions on Design Automation of Electronic Systems

DOI: 10.1145/3774883

Authors: Tianji Liu, Nutdranai Jaruthikorn, Shiju Lin, Bentian Jiang, Guannan Guo, Weihua Sheng, Evangeline F.Y. Young

Institutions: Chinese University of Hong Kong, Hong Kong University of Science and Technology, The Hong Kong University of Science and Technology (Guangzhou), Huawei Technologies (China)

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: hybrid

OpenAlex ID: W4415915096

FWCI:

Cites: 21

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