Simplification of Via-first TSV and Backside Interconnect Process for Large-Scale Superconducting Quantum Annealing Circuits
Year: 2025
Type: article
Abstract: We proposed a simplified through-silicon via (TSV) and backside interconnect process to suppress cavity resonance in superconducting quantum annealing circuits. The conventional process consisted of 13 steps, but in the new process, it was reduced to 11 steps by forming TSVs first, then creating the backside interconnect, and finally thinning the wafer to expose the TSVs. The new process comprised the following steps: (a) deep silicon etching using the Bosch process, (b) hole cleaning to remove the photoresist and fluoropolymer residues, (c) CF4 plasma treatment to reduce sidewall scallop, (d) barrier/seed-layer deposition, (e) copper electroplating for TSV filling, (f) backside chemical mechanical polishing (CMP), (g) formation of the superconducting backside interconnect (Ti-Nb-Ti layer), (h) deposition of a backside protection layer, (i) direct Si/Cu grinding, (j) frontside CMP, and (k) fabrication of the quantum annealing circuit. Using this process, we fabricated TSVs (diameter at backside, 60 μm; depth, 395 μm) with superconducting backside interconnects in a 100-mm high-resistivity silicon wafer. Furthermore, we evaluated the effect of TSVs on cavity resonance through high-frequency measurements of samples with and without TSVs. The results demonstrate that the TSVs and backside interconnect of new process effectively suppress cavity resonance.
Source: IMAPSource Proceedings
DOI: 10.4071/001c.147098
Authors: Naoya Watanabe, Yuuki Araga, Ayuka Morioka, Kunihiko Ishihara, Tomohiro Nishiyama, Katsuya Kikuchi
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4416293953
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