Year: 2025
Type: article
Abstract: This paper introduces a unique dual-port RAM design that targets both power efficiency and timing performance optimization. The new architecture merges the sophisticated clock gating and the data-transfer pipeline techniques, which make clocks on and off as per the need thus reducing the dynamic power to the most minimum while still using the pipelining technique to its full advantage for throughput and stabilization of timing. In contrast to the classical dual-port RAMs, this design has the simultaneous read and write feature without the energy cost that is traditionally associated with it. The system which is built in Verilog HDL and runs on FPGA platforms overcomes port conflicts by using techniques of port locking and priority management. The results of the tests indicate that there are major savings in power without any degradation in the functional performance, hence this dual-port RAM can be particularly utilized in the applications where efficient parallel memory operation under a strict power constraint is also required. The power-optimized RAM module with robust conflict resolution that is one of the contributions of this work is already showing its potential for high-speed, low-power applications.
Authors: Matta Yashwanth Reddy, G. Sujatha
Institution: Sri Venkateswara College of Engineering Tirupati
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4416397699