Year: 2025
Type: article
Abstract: Ring Oscillators (ROs) are widely used in FPGA-based applications such as hardware security, true random number generation, and clock generation, but conventional carry-chain-based oscillators suffer from high power consumption, limited frequency tunability, and inefficient FPGA resource utilization. This paper proposes a Hybrid Carry Chain and LUT-Based Ring Oscillator architecture that combines the speed of carry chains with the flexibility of LUT- based delay elements. The design is modeled and implemented on a Xilinx FPGA platform using the Vivado toolchain, and its performance is evaluated through power analysis, resource utilization, and oscillation frequency measurements. Simulation and hardware validation results demonstrate a 63% reduction in power consumption (from 0.334 W to 0.122 W) and an 80% reduction in LUT usage (from 10 to 2) compared to the conventional design, while maintaining stable and tunable oscillation frequency. The contributions of this work include a low-power and resource-efficient FPGA oscillator design, enhanced frequency control through hybrid delay elements, and experimental verification that highlights its suitability for IoT devices, lightweight cryptography, and energy-constrained hardware security systems.
Authors: Godugupalli Mounika, C. Chandrasekhar
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
OpenAlex ID: W4416452563