Year: 2025
Type: conference-paper
Abstract: This work presents a two-stage digital twin methodology for developing and validating DFL algorithms on resource-constrained microcontrollers. The first stage, our simulation-based twin, enables rapid prototyping and algorithm exploration without hardware constraints, while the second stage, based on leveraging several hardware emulation instances in a containerized environment, provides hardware-aware validation under realistic conditions including network delays, resource limitations, and communication protocols. This approach bridges the critical gap between research and deployment, enabling performance analysis at a pace impractical with physical hardware alone. We demonstrate how this digital twin pipeline is essential for robust Machine Learning Operations (MLOps) in IoT environments, allowing for scalable, cost-effective testing of decentralized tiny ML. Our results across simulation, emulation, and a cluster of real ESP32-S3 microcontrollers show that our twins faithfully reproduce physical device behavior, making it a valuable framework for advancing tiny, decentralized AI.
Language: English
Topic: IoT and Edge/Fog Computing
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4416477626