Numerical Study of the Impact of Inter-Die Thermal Conductance on the Thermal Performance of 3D ICs Cooled by a Single-Layer Microchannel Heat Exchanger
Year: 2025
Type: article
Abstract: Current manufacturing trends in 3D integration are resulting in a notorious increase in power density, and the use of conventional cooling methods may not be sufficient for cooling future 3D ICs with several chip dies. Moreover, with very thin chip dies, implementing alternative cooling methods based on etching microchannels in every chip die may not be technologically feasible. In this study, we suggest implementing microchannels only in the top, unthinned layer of silicon. In this case, the crucial parameter influencing cooling efficiency is the thermal conductance between vertically stacked chip dies. Therefore, an extensive numerical study is conducted, which quantifies the thermal performance of such single-layer microchannel heat exchangers as a function of inter-die thermal conductance, in addition to other chip parameters. Several important conclusions are presented based on these analyses. In particular, for various 3D stacks, this study allows the determination of the concrete threshold values of inter-die thermal conductance relative to which thermal performance degradation starts to become significant.
Source: Energies
DOI: 10.3390/en18236150
Authors: Piotr Zając, Wojciech Zabierowski
Institution: Lodz University of Technology
Language: English
Topic: 3D IC and TSV technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $3,137
OpenAlex ID: W4416593231