Enhanced Logic‐In‐Memory Systems with Recessed‐Source/Drain Feedback Field Effect Transistors
Year: 2025
Type: article
Abstract: This article presents binary and ternary logic in memory (LIM) systems implementations using recessed‐source/drain feedback field effect (Re‐S/D SOI FBFET) Transistors. The Re‐S/D SOI FBFET offers several advantages, including a high I ON current and an almost zero steep subthreshold swing (SS), making it useful for both logic and memory applications. The Re‐S/D SOI FBFET's main advantage lies in its improved voltage swing. The retention times for inverter input logic “1,” and “−1” are 8.5 and 102 s, respectively. Similarly, for NAND and NOR gates with inputs of “00”, “11”, and "−1−1”, the corresponding retention times are 74.9, 3.6, and 60.8 s for NAND, and 60, 53.3, and 135 s for NOR, without standby power consumption. These logic gates exhibit less energy compared with the other devices and could overcome the issue of voltage mismatch during cascading. Silvaco ATLAS was used for device and mixed‐mode circuit simulations. This study reveals the future potential of Re‐S/D SOI FBFET in advancing multivalued logic and memory systems.
Source: physica status solidi (a)
Institution: National Institute of Technology Calicut
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W4416610146