Year: 2025
Type: article
Abstract: Despite growing interest in virtualization of Field-Programmable Gate Arrays (FPGAs), existing approaches predominantly target datacenter-class FPGAs, which heavily rely on external (powerful) servers for hypervisor execution and resource management. This significantly limits their suitability for edge environments where autonomy, energy efficiency, and direct low-latency access to physical Input/Output (I/O) are critical. To address this goal, this paper introduces µ-VF, a lightweight virtualization framework specifically designed to enable robust multi-tenancy on embedded FPGAs operating autonomously at the network edge. µ-VF embeds all virtualization logic entirely onboard the FPGA unit, eliminating the need for any off-chip infrastructure and thus significantly reducing overall system power consumption. Each tenant operates within a secure and isolated container on the on-chip Processing System (PS), coupled with exclusive access to a dedicated Programmable Logic (PL) region. Additionally, µ-VF fully virtualizes external General-Purpose Input/Output (GPIO) directly within the PL fabric, thus enabling independent, concurrent and latency-sensitive access to shared peripherals. We have implemented a prototype of µ-VF with a Zynq UltraScale+ ZCU102 board with PL operating at 100 MHz. Experimental results demonstrate that the hardware virtualization layer utilizes less than 10% of the FPGA's logic resources, with 85% available for tenant applications compared to 50% in prior work. Moreover, µ-VF adds 2.93% to Memory-Mapped I/O (MMIO) access latency compared to native execution for single-tenant operation, increasing to 6.5% with four concurrent tenants. Memory throughput measurements show 1.8% overhead for write operations and negligible impact on read operations, with aggregate throughput 17.1% higher than previous frameworks. Hardware-based GPIO remapping completes in 20 nanoseconds.
DOI: 10.1145/3771581
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: bronze
Funders: National Science Foundation, European Commission, European Union Agency for Network and Information Security, Defense Advanced Research Projects Agency, Advanced Research Projects Agency, Office of Naval Research, Division of Electrical, Communications and Cyber Systems, Air Force Office of Scientific Research
Awards: G1418398344, G1483026471, G1793443292, G1869219662, G1935467843, G3120737655, CCF: SHF: Small: Self-Adaptive Interference-Avoiding Wireless Receiver Hardware through Real-Time Learning-Based Automatic Optimization of Power-Efficient Integrated Circuits, G507880695, G595188498, G6098521345, G6114848347, G7083697840, Collaborative Research: FuSe: Deep Learning and Signal Processing using Silicon Photonics and Digital CMOS Circuits for Ultra-Wideband Spectrum Perception, G8876996369, G8927239830, Collaborative Research: SWIFT: AI-based Sensing for Improved Resiliency via Spectral Adaptation with Lifelong Learning
OpenAlex ID: W4416927415